It provides a good fan-out but cannot be connected to other TLL outputs as can open-collector outputs. The output stage has the property of providing a low-impedance drive for both positive and negative signals. types of output configuration: Open collector output, totem-pole output and three state. The output stage, consisting of Q 3, D 1, Q 4, and R, acts as a power amplifier and is often termed a totem-pole output. The standard TTL gate was the first version in the TTL family. Diode D 1 is included to establish the correct bias conditions for Q 4. The output thus increases to +5 volts, i.e. No current is available via Q 2 for Q 3's base, and so Q 3 turns off. If any one of the Q 1 inputs is returned to logic 0, 0 volts, then Q 1 is turned hard on, turning off Q 2 whose collector voltage rises this turns on Q 4. The emitter voltage of Q 2 rises while its collector voltage falls, turning Q 3 on and Q 4 off. Thus if all inputs are at a high voltage (logic 1), all input “diodes” are reverse biased the collector voltage of Q 1 rises to V cc, turning on Q 2 (which acts as a phase splitter). Each base-emitter junction of Q 1 effectively acts as a diode, in a similar manner to a DTL input stage. The basic circuit uses a multiemitter bipolar transistor, Q 1, which is easily fabricated in integrated-circuit form. The diagram shows the equivalent circuit of a TTL two-input NAND gate. Only reverse saturation current will be drained from Vcc, and the drop across R4 will be vey small. If either one or both inputs are at logic 0 Q4 (the pull-down transistor) will be of in the cutoff region and it will not conduct. It is available in low power and high switching speed versions (see Schottky TTL), in addition to the standard form. Use of Totem-Pole output Eliminate pull-up transistor Q3 and the Diode, still the circuit works as a 2-input NAND gate. A widely used family of logic circuits that is produced in integrated-circuit form and whose principal switching components are bipolar transistors. The operation is the same as the 2-input TTL NAND gate.Abbrev. It is the same as that we discussed in the 2-input TTL NAND gate circuit, except that here, the input transistor Q 1 has three emitters instead of two. 7400) is obsolete Newer TTL families still used (e.g. The following figure shows the circuit of the standard 3-input TTL NAND gate. Bipolar Transistor- Transistor Logic (TTL) first introduced by in 1964 (Texas Instruments) TTL has shaped digital technology in many ways Standard TTL family (e.g. Circuit of standard 3-input TTL NAND Gate With Q 2 turned ON, transistor Q 4 will also be turned ON.īoth the transistors at the output side will conduct and so the output at terminal will have LOW value, which is considered as logic 0. The diode D C at the collector-base junction is forward biased. When both the inputs A and B are high, both the diodes at the emitter-base junction will be reverse biased. The same operation will take place as explained above. When any one input, either A or B is low, the diode with low input will be forward biased. Since Q 3 is an emitter follower, the output at the terminal will also be HIGH, which is at logic 1. With Q 2 open, the transistor Q 4 will also cut off. The supply voltage gets dropped in the resistor R 1 and it will not be sufficient to turn ON the transistor Q 2. So the current due to the supply voltage +V CC = 5 V will go to the ground through R 1 and the two diodes D A and D B. When both inputs A and B are low, both the diodes are forward biased. Diode D C represents the collector-base junction of transistor Q 2. In the figure, diodes, D A and D B represent the 2-input emitter junction of transistor Q 1.